In a multicore system, there are several shared resources. One of the most common shared resources is SRAM and typically the design expectation is that it is accessible with zero -wait latency. In such a system, simple fixed priority or round robin scheme may be used to arbitrate accesses from the CPU or masters. However, sharing memory adds overhead in meeting higher clock speeds. One such critical path is generation of a stall signal (READY) to CPU or master. When multiple masters are accessing the same resource, the stall signal of a given CPU depends on accesses from the other masters. This creates long timing paths from one master to other and these paths limit maximum clock speed of the system that can be achieved.